In a recent blog post Intel has made some bold claims about its new PowerVia technology, and how it’s been performing in Meteor Lake-based test chips, delivering a greater than 5% increase to clock speeds. According to Intel’s Ben Sell, vice pres. of technology development, that puts PowerVia on track for delivery next year along with the Intel 20A process node. 

PowerVia represents a new way to create processors, effectively sandwiching the transistors in the middle of the chip, with the interconnects to the outside world on the front and the power wiring on the back. This so-called backside power delivery is a big shift in semiconductor manufacturing and at once simplifies, complicates, and alleviates issues with the ever-shrinking of transistors and processors.

PowerVia is going to be first sampled in the upcoming Arrow Lake generation of Intel processors (presumably 15th Gen Core) which is due in 2024 on the Intel 20A production process. But in order to speed up the development process it was decoupled from the design of the 20A process node itself.

In fact Intel has shown the functional benefits of the technology on a “Frankenstein test-chip” called Blue Sky Creek. In reality it’s a Meteor Lake-based chip using the upcoming generation’s Efficient-core, built on the Intel 4 process, but incorporating the PowerVia tech.

Just from the addition of backside power delivery, Intel claims that it has managed to add more than 5% frequency improvement to the test chip. If we take the clock speed of the Raptor Lake E-cores as a starting point, that would mean a change from 4.3GHz to 4.5GHz just from shifting around where the interconnects and power wiring goes.

Traditionally, chips are built like pizzas (Intel’s word, not mine), with the core transistors on the bottom and everything else layered on top, with the power and other interconnects in the final layer. It’s then flipped over, and stuck in a package that sits in your motherboard socket to maintain its connection to the outside world.

With backside power delivery, and therefore in Intel’s PowerVia, it’s more like a sandwich. With the transistors in the middle, the interconnect layer on top, and the power connections on the back behind the transistors. 

That’s a drastic over-simplification of what Intel has done with PowerVia, but in reality what it means is there is more space for using larger connections with greater distance between them. As transistors keep shrinking and more of them get jammed onto a chip, the mass of power and interconnect wiring layered on top of the pizza-chip means interference and power and signals fade in the chaos. 

The simplification inherent in separating things out is as much a benefit for the power as it is for the interconnects; “you get better power delivery and you get better signal wiring,” says Sell.

Intel isn’t the only one doing this; backside power delivery is something all chipmakers are looking into as nodes get smaller. But Intel claims that with PowerVia coming online along with its RibbonFET (or gate all-around) technology in its 20A process, that will put the competition “roughly two years behind” when it comes to backside power delivery.